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library ieee;
use ieee.std_logic_1164.all;

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entity cmp_and is
port(  	A:	in std_logic;
	B:	in std_logic;
	F:	out std_logic
);
end cmp_and;

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architecture behv of cmp_and is
begin
  process(A,B)
  begin
    F <= A and B;
  end process;
end behv;
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